//*****************************************************************************
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
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// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : 3.5
//  \   \        Application        : MIG
//  /   /        Filename           : sim_tb_top.v
// /___/   /\    Date Last Modified : $Date: 2010/04/22 12:17:54 $
// \   \  /  \   Date Created       : Mon Mar 2 2009
//  \___\/\___\
//
// Device      : Spartan-6
// Design Name : DDR/DDR2/DDR3/LPDDR
// Purpose     : This is the simulation testbench which is used to verify the
//               design. The basic clocks and resets to the interface are
//               generated here. This also connects the memory interface to the
//               memory model.
//*****************************************************************************

`timescale 1ps/1ps
module sim_tb_top;

// ========================================================================== //
// Parameters                                                                 //
// ========================================================================== //
   parameter DEBUG_EN              = 0;   
    
   parameter C1_MEMCLK_PERIOD     = 3333;
   parameter C1_RST_ACT_LOW        = 0;
   parameter C1_INPUT_CLK_TYPE     = "DIFFERENTIAL";
   parameter C1_NUM_DQ_PINS        = 16;
   parameter C1_MEM_ADDR_WIDTH     = 13;
   parameter C1_MEM_BANKADDR_WIDTH = 3;   
   parameter C1_MEM_ADDR_ORDER     = "BANK_ROW_COLUMN"; 
      
   parameter C1_P0_MASK_SIZE       = 8;
   parameter C1_P0_DATA_PORT_SIZE  = 64;  
   parameter C1_P1_MASK_SIZE       = 8;
   parameter C1_P1_DATA_PORT_SIZE  = 64;
   parameter C1_MEM_BURST_LEN     = 4;
   parameter C1_MEM_NUM_COL_BITS   = 10;
   parameter C1_CALIB_SOFT_IP      = "TRUE";  
   parameter C1_SIMULATION      = "TRUE";
   parameter C1_HW_TESTING      = "FALSE";
   
   
   localparam C1_p0_BEGIN_ADDRESS                   = (C1_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000200;
   localparam C1_p0_DATA_MODE                       = 4'b0010;
   localparam C1_p0_END_ADDRESS                     = (C1_HW_TESTING == "TRUE") ? 32'h02ffffff:32'h000003ff;
   localparam C1_p0_PRBS_EADDR_MASK_POS             = (C1_HW_TESTING == "TRUE") ? 32'hfc000000:32'hfffff800;
   localparam C1_p0_PRBS_SADDR_MASK_POS             = (C1_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000200;
   localparam C1_p1_BEGIN_ADDRESS                   = (C1_HW_TESTING == "TRUE") ? 32'h03000000:32'h00000400;
   localparam C1_p1_DATA_MODE                       = 4'b0010;
   localparam C1_p1_END_ADDRESS                     = (C1_HW_TESTING == "TRUE") ? 32'h04ffffff:32'h000005ff;
   localparam C1_p1_PRBS_EADDR_MASK_POS             = (C1_HW_TESTING == "TRUE") ? 32'hf8000000:32'hfffff000;
   localparam C1_p1_PRBS_SADDR_MASK_POS             = (C1_HW_TESTING == "TRUE") ? 32'h03000000:32'h00000400;


// ========================================================================== //
// Dump waveform,fsdb dump                                                       //
// ========================================================================== //
`ifdef FSDB_DUMP
initial
  begin
    $fsdbDumpfile("verilog.fsdb");
    $fsdbDumpvars(0,sim_tb_top);
  end
`else
`endif
// ========================================================================== //
// Signal Declarations                                                        //
// ========================================================================== //

// Clocks

   reg                              c1_sys_clk;
   wire                             c1_sys_clk_p;
   wire                             c1_sys_clk_n;
   
   reg                              fruc_clk;//36MHz
   reg                              me_clk  ;//72MHz
// System Reset
   reg                              c1_sys_rst;
   wire                             c1_sys_rst_n;
    
   reg                              fruc_rstj;


// Design-Top Port Map
   wire                             c1_error;
   wire                             c1_calib_done;
   wire [31:0]                      c1_cmp_data;
   wire                             c1_cmp_error;

   wire [C1_MEM_ADDR_WIDTH-1:0]     mcb1_dram_a; 
   wire [C1_MEM_BANKADDR_WIDTH-1:0] mcb1_dram_ba;      
   wire                             mcb1_dram_ck;      
   wire                             mcb1_dram_ck_n;    
   wire [C1_NUM_DQ_PINS-1:0]        mcb1_dram_dq;      
   wire                             mcb1_dram_dqs;     
   wire                             mcb1_dram_dqs_n;   
   wire                             mcb1_dram_dm;      
   wire                             mcb1_dram_ras_n;   
   wire                             mcb1_dram_cas_n;   
   wire                             mcb1_dram_we_n;    
   wire                             mcb1_dram_cke;     
   wire                             mcb1_dram_odt;     
                                                       
   wire [191:0]                     c1_error_status;   
   wire                             mcb1_dram_udqs;    // for X16 parts
   wire                             mcb1_dram_udqs_n;  // for X16 parts
   wire                             mcb1_dram_udm;     // for X16 parts


// User design  Sim
  wire                              c1_clk0;
  wire                              c1_rst0;

  wire                              c1_p0_cmd_en;
  wire [2:0]                        c1_p0_cmd_instr;
  wire [5:0]                        c1_p0_cmd_bl;
  wire [29:0]                       c1_p0_cmd_byte_addr;
  wire                              c1_p0_cmd_empty;
  wire                              c1_p0_cmd_full;
  wire                              c1_p0_wr_en;
  wire [C1_P0_MASK_SIZE - 1:0]      c1_p0_wr_mask;//7:0
  wire [C1_P0_DATA_PORT_SIZE - 1:0] c1_p0_wr_data;//63:0
  wire                              c1_p0_wr_full;
  wire                              c1_p0_wr_empty;
  wire [6:0]                        c1_p0_wr_count;
  wire                              c1_p0_wr_underrun;
  wire                              c1_p0_wr_error;
  wire                              c1_p0_rd_en;
  wire [C1_P0_DATA_PORT_SIZE - 1:0] c1_p0_rd_data;//63:0
  wire                              c1_p0_rd_full;
  wire                              c1_p0_rd_empty;
  wire [6:0]                        c1_p0_rd_count;
  wire                              c1_p0_rd_overflow;
  wire                              c1_p0_rd_error;

  wire                              c1_p1_cmd_en;
  wire [2:0]                        c1_p1_cmd_instr;
  wire [5:0]                        c1_p1_cmd_bl;
  wire [29:0]                       c1_p1_cmd_byte_addr;
  wire                              c1_p1_cmd_empty;
  wire                              c1_p1_cmd_full;
  wire                              c1_p1_wr_en;
  wire [C1_P1_MASK_SIZE - 1:0]      c1_p1_wr_mask;//7:0
  wire [C1_P1_DATA_PORT_SIZE - 1:0] c1_p1_wr_data;//63:0
  wire                              c1_p1_wr_full;
  wire                              c1_p1_wr_empty;
  wire [6:0]                        c1_p1_wr_count;
  wire                              c1_p1_wr_underrun;
  wire                              c1_p1_wr_error;
  wire                              c1_p1_rd_en;
  wire [C1_P1_DATA_PORT_SIZE - 1:0] c1_p1_rd_data;//63:0
  wire                              c1_p1_rd_full;
  wire                              c1_p1_rd_empty;
  wire [6:0]                        c1_p1_rd_count;
  wire                              c1_p1_rd_overflow;
  wire                              c1_p1_rd_error;
 


// Error & Calib Signals
   wire                             error;
   wire                             calib_done;
   wire                             rzq1;
     

   
// ========================================================================== //
// Clocks Generation                                                          //
// ========================================================================== //
parameter ME_PERIOD     = 5000;//72MHz

   initial
      c1_sys_clk = 1'b0;
   always
      #(C1_MEMCLK_PERIOD/2) c1_sys_clk = ~c1_sys_clk;//300MHz

   assign                c1_sys_clk_p = c1_sys_clk;
   assign                c1_sys_clk_n = ~c1_sys_clk;

    initial 
        me_clk = 1'b0;
    always
        me_clk = #ME_PERIOD ~me_clk;
        
    initial 
        fruc_clk = 1'b0;
    always @(posedge me_clk)
        fruc_clk <= ~fruc_clk;//36MHz

reg  fruc1_clk;

    initial 
        fruc1_clk = 1'b0;
    always @(posedge fruc_clk)
        fruc1_clk <= ~fruc1_clk;//36MHz
// ========================================================================== //
// Reset Generation                                                           //
// ========================================================================== //
 
   initial begin   
      c1_sys_rst = 1'b1;
      #100;
      c1_sys_rst = 1'b0;        
      #20000;
      c1_sys_rst = 1'b1;
   end
   assign c1_sys_rst_n = C1_RST_ACT_LOW ? c1_sys_rst : ~c1_sys_rst;

   initial begin
        fruc_rstj = 1'b1;
        #200;
        fruc_rstj = 1'b0;
        #20000;
        fruc_rstj = 1'b1;
   end 

// ========================================================================== //
// Error Grouping                                                           //
// ========================================================================== //

assign error = c1_error;
assign calib_done = c1_calib_done;

//wire   rzq1 = 1;
PULLDOWN rzq_pulldown1 (.O(rzq1));

// ========================================================================== //
// user define test                                                         //
// ========================================================================== //
//`define SYSY_TEST

`ifdef SYSY_TEST
`else
wire          test_cmd_en         ;
wire [2:0]    test_cmd_instr      ;
wire [5:0]    test_cmd_bl         ;
wire [29:0]   test_cmd_byte_addr  ;
wire          test_cmd_empty      ;
wire          test_cmd_full       ;
wire          test_wr_en          ;
wire [7:0]    test_wr_mask        ;//7:0
wire [63:0]   test_wr_data        ;//63:0
wire          test_wr_full        ;
wire          test_wr_empty       ;
wire [6:0]    test_wr_count       ;
wire          test_wr_underrun    ;
wire          test_wr_error       ;
wire          test_rd_en          ;
wire [63:0]   test_rd_data        ;//63:0
wire          test_rd_full        ;
wire          test_rd_empty       ;
wire [6:0]    test_rd_count       ;
wire          test_rd_overflow    ;
wire          test_rd_error       ;


wire          test1_cmd_en         ;
wire [2:0]    test1_cmd_instr      ;
wire [5:0]    test1_cmd_bl         ;
wire [29:0]   test1_cmd_byte_addr  ;
wire          test1_cmd_empty      ;
wire          test1_cmd_full       ;
wire          test1_wr_en          ;
wire [7:0]    test1_wr_mask        ;//7:0
wire [63:0]   test1_wr_data        ;//63:0
wire          test1_wr_full        ;
wire          test1_wr_empty       ;
wire [6:0]    test1_wr_count       ;
wire          test1_wr_underrun    ;
wire          test1_wr_error       ;
wire          test1_rd_en          ;
wire [63:0]   test1_rd_data        ;//63:0
wire          test1_rd_full        ;
wire          test1_rd_empty       ;
wire [6:0]    test1_rd_count       ;
wire          test1_rd_overflow    ;
wire          test1_rd_error       ;

dram_access dram_access_test(
   .fruc_clk            (fruc_clk            ),
   .fruc_rstj           (fruc_rstj           ),
   
   .c1_calib_done       (c1_calib_done       ),
   
   .test_st_addr        (30'h0          ),
   .test_cmd_en         (test_cmd_en         ),  
   .test_cmd_instr      (test_cmd_instr      ),  
   .test_cmd_bl         (test_cmd_bl         ),  
   .test_cmd_byte_addr  (test_cmd_byte_addr  ),  
   .test_cmd_empty      (test_cmd_empty      ),  
   .test_cmd_full       (test_cmd_full       ),  
   .test_wr_en          (test_wr_en          ),  
   .test_wr_mask        (test_wr_mask        ),
   .test_wr_data        (test_wr_data        ),
   .test_wr_full        (test_wr_full        ),  
   .test_wr_empty       (test_wr_empty       ),  
   .test_wr_count       (test_wr_count       ),  
   .test_wr_underrun    (test_wr_underrun    ),  
   .test_wr_error       (test_wr_error       ),  
   .test_rd_en          (test_rd_en          ),  
   .test_rd_data        (test_rd_data        ),
   .test_rd_full        (test_rd_full        ),
   .test_rd_empty       (test_rd_empty       ),  
   .test_rd_count       (test_rd_count       ),  
   .test_rd_overflow    (test_rd_overflow    ),  
   .test_rd_error       (test_rd_error       )
    );

dram_access dram_access_test1(
   .fruc_clk            (fruc1_clk            ),
   .fruc_rstj           (fruc_rstj           ),
   
   .c1_calib_done       (c1_calib_done       ),
   
   .test_st_addr        (30'h7ff_0000        ),
   .test_cmd_en         (test1_cmd_en         ),  
   .test_cmd_instr      (test1_cmd_instr      ),  
   .test_cmd_bl         (test1_cmd_bl         ),  
   .test_cmd_byte_addr  (test1_cmd_byte_addr  ),  
   .test_cmd_empty      (test1_cmd_empty      ),  
   .test_cmd_full       (test1_cmd_full       ),  
   .test_wr_en          (test1_wr_en          ),  
   .test_wr_mask        (test1_wr_mask        ),
   .test_wr_data        (test1_wr_data        ),
   .test_wr_full        (test1_wr_full        ),  
   .test_wr_empty       (test1_wr_empty       ),  
   .test_wr_count       (test1_wr_count       ),  
   .test_wr_underrun    (test1_wr_underrun    ),  
   .test_wr_error       (test1_wr_error       ),  
   .test_rd_en          (test1_rd_en          ),  
   .test_rd_data        (test1_rd_data        ),
   .test_rd_full        (test1_rd_full        ),
   .test_rd_empty       (test1_rd_empty       ),  
   .test_rd_count       (test1_rd_count       ),  
   .test_rd_overflow    (test1_rd_overflow    ),  
   .test_rd_error       (test1_rd_error       )
    );
    
`endif
// ========================================================================== //
// DESIGN TOP INSTANTIATION                                                    //
// ========================================================================== //

fruc_memc #(

.C1_P0_MASK_SIZE       (C1_P0_MASK_SIZE      ),
.C1_P0_DATA_PORT_SIZE  (C1_P0_DATA_PORT_SIZE ),
.C1_P1_MASK_SIZE       (C1_P1_MASK_SIZE      ),
.C1_P1_DATA_PORT_SIZE  (C1_P1_DATA_PORT_SIZE ),

.C1_MEMCLK_PERIOD      (C1_MEMCLK_PERIOD    ),
.C1_RST_ACT_LOW        (C1_RST_ACT_LOW      ),
.C1_INPUT_CLK_TYPE     (C1_INPUT_CLK_TYPE   ),

 
.DEBUG_EN              (DEBUG_EN),

.C1_MEM_ADDR_ORDER     (C1_MEM_ADDR_ORDER    ),
.C1_NUM_DQ_PINS        (C1_NUM_DQ_PINS       ),
.C1_MEM_ADDR_WIDTH     (C1_MEM_ADDR_WIDTH    ),
.C1_MEM_BANKADDR_WIDTH (C1_MEM_BANKADDR_WIDTH),

.C1_SIMULATION         (C1_SIMULATION       ),
.C1_CALIB_SOFT_IP      (C1_CALIB_SOFT_IP    )
)
fruc_memc (
  .c1_sys_clk_p           (c1_sys_clk_p),
  .c1_sys_clk_n           (c1_sys_clk_n),
  .c1_sys_rst_n           (c1_sys_rst_n),                        

  .mcb1_dram_dq           (mcb1_dram_dq),  
  .mcb1_dram_a            (mcb1_dram_a),  
  .mcb1_dram_ba           (mcb1_dram_ba),
  .mcb1_dram_ras_n        (mcb1_dram_ras_n),                        
  .mcb1_dram_cas_n        (mcb1_dram_cas_n),                        
  .mcb1_dram_we_n         (mcb1_dram_we_n),                          
  .mcb1_dram_odt          (mcb1_dram_odt),
  .mcb1_dram_cke          (mcb1_dram_cke),                          
  .mcb1_dram_ck           (mcb1_dram_ck),                          
  .mcb1_dram_ck_n         (mcb1_dram_ck_n),       
  .mcb1_dram_dqs          (mcb1_dram_dqs),                          
  .mcb1_dram_dqs_n        (mcb1_dram_dqs_n),
  .mcb1_dram_udqs         (mcb1_dram_udqs),    // for X16 parts                        
  .mcb1_dram_udqs_n       (mcb1_dram_udqs_n),  // for X16 parts
  .mcb1_dram_udm          (mcb1_dram_udm),     // for X16 parts
  .mcb1_dram_dm           (mcb1_dram_dm),
    
  .c1_clk0                (c1_clk0),
  .c1_rst0                (c1_rst0),
    
//  .c1_clk0                (fruc_clk),
//  .c1_rst0                (fruc_rstj),
 
  .c1_calib_done          (c1_calib_done),
  .mcb1_rzq               (rzq1),



`ifdef SYSY_TEST           
   .c1_p0_cmd_clk                          (c1_clk0),
   .c1_p0_cmd_en                           (c1_p0_cmd_en),
   .c1_p0_cmd_instr                        (c1_p0_cmd_instr),
   .c1_p0_cmd_bl                           (c1_p0_cmd_bl),
   .c1_p0_cmd_byte_addr                    (c1_p0_cmd_byte_addr),
   .c1_p0_cmd_empty                        (c1_p0_cmd_empty),
   .c1_p0_cmd_full                         (c1_p0_cmd_full),
   .c1_p0_wr_clk                           (c1_clk0),
   .c1_p0_wr_en                            (c1_p0_wr_en),
   .c1_p0_wr_mask                          (c1_p0_wr_mask),
   .c1_p0_wr_data                          (c1_p0_wr_data),
   .c1_p0_wr_full                          (c1_p0_wr_full),
   .c1_p0_wr_empty                         (c1_p0_wr_empty),
   .c1_p0_wr_count                         (c1_p0_wr_count),
   .c1_p0_wr_underrun                      (c1_p0_wr_underrun),
   .c1_p0_wr_error                         (c1_p0_wr_error),
   .c1_p0_rd_clk                           (c1_clk0),
   .c1_p0_rd_en                            (c1_p0_rd_en),
   .c1_p0_rd_data                          (c1_p0_rd_data),
   .c1_p0_rd_full                          (c1_p0_rd_full),
   .c1_p0_rd_empty                         (c1_p0_rd_empty),
   .c1_p0_rd_count                         (c1_p0_rd_count),
   .c1_p0_rd_overflow                      (c1_p0_rd_overflow),
   .c1_p0_rd_error                         (c1_p0_rd_error),
       
   .c1_p1_cmd_clk                          (c1_clk0),
   .c1_p1_cmd_en                           (c1_p1_cmd_en),
   .c1_p1_cmd_instr                        (c1_p1_cmd_instr),
   .c1_p1_cmd_bl                           (c1_p1_cmd_bl),
   .c1_p1_cmd_byte_addr                    (c1_p1_cmd_byte_addr),
   .c1_p1_cmd_empty                        (c1_p1_cmd_empty),
   .c1_p1_cmd_full                         (c1_p1_cmd_full),
   .c1_p1_wr_clk                           (c1_clk0),
   .c1_p1_wr_en                            (c1_p1_wr_en),
   .c1_p1_wr_mask                          (c1_p1_wr_mask),
   .c1_p1_wr_data                          (c1_p1_wr_data),
   .c1_p1_wr_full                          (c1_p1_wr_full),
   .c1_p1_wr_empty                         (c1_p1_wr_empty),
   .c1_p1_wr_count                         (c1_p1_wr_count),
   .c1_p1_wr_underrun                      (c1_p1_wr_underrun),
   .c1_p1_wr_error                         (c1_p1_wr_error),
   .c1_p1_rd_clk                           (c1_clk0),
   .c1_p1_rd_en                            (c1_p1_rd_en),
   .c1_p1_rd_data                          (c1_p1_rd_data),
   .c1_p1_rd_full                          (c1_p1_rd_full),
   .c1_p1_rd_empty                         (c1_p1_rd_empty),
   .c1_p1_rd_count                         (c1_p1_rd_count),
   .c1_p1_rd_overflow                      (c1_p1_rd_overflow),
   .c1_p1_rd_error                         (c1_p1_rd_error) 
`else
   .c1_p0_cmd_clk                          (fruc_clk),
   .c1_p0_cmd_en                           (test_cmd_en),
   .c1_p0_cmd_instr                        (test_cmd_instr),
   .c1_p0_cmd_bl                           (test_cmd_bl),
   .c1_p0_cmd_byte_addr                    (test_cmd_byte_addr),
   .c1_p0_cmd_empty                        (test_cmd_empty),
   .c1_p0_cmd_full                         (test_cmd_full),
   .c1_p0_wr_clk                           (fruc_clk),
   .c1_p0_wr_en                            (test_wr_en),
   .c1_p0_wr_mask                          (test_wr_mask),
   .c1_p0_wr_data                          (test_wr_data),
   .c1_p0_wr_full                          (test_wr_full),
   .c1_p0_wr_empty                         (test_wr_empty),
   .c1_p0_wr_count                         (test_wr_count),
   .c1_p0_wr_underrun                      (test_wr_underrun),
   .c1_p0_wr_error                         (test_wr_error),
   .c1_p0_rd_clk                           (fruc_clk),
   .c1_p0_rd_en                            (test_rd_en),
   .c1_p0_rd_data                          (test_rd_data),
   .c1_p0_rd_full                          (test_rd_full),
   .c1_p0_rd_empty                         (test_rd_empty),
   .c1_p0_rd_count                         (test_rd_count),
   .c1_p0_rd_overflow                      (test_rd_overflow),
   .c1_p0_rd_error                         (test_rd_error),
   
  
   
   .c1_p1_cmd_clk                          (fruc1_clk),
   .c1_p1_cmd_en                           (test1_cmd_en),
   .c1_p1_cmd_instr                        (test1_cmd_instr),
   .c1_p1_cmd_bl                           (test1_cmd_bl),
   .c1_p1_cmd_byte_addr                    (test1_cmd_byte_addr),
   .c1_p1_cmd_empty                        (test1_cmd_empty),
   .c1_p1_cmd_full                         (test1_cmd_full),
   .c1_p1_wr_clk                           (fruc1_clk),
   .c1_p1_wr_en                            (test1_wr_en),
   .c1_p1_wr_mask                          (test1_wr_mask),
   .c1_p1_wr_data                          (test1_wr_data),
   .c1_p1_wr_full                          (test1_wr_full),
   .c1_p1_wr_empty                         (test1_wr_empty),
   .c1_p1_wr_count                         (test1_wr_count),
   .c1_p1_wr_underrun                      (test1_wr_underrun),
   .c1_p1_wr_error                         (test1_wr_error),
   .c1_p1_rd_clk                           (fruc1_clk),
   .c1_p1_rd_en                            (test1_rd_en),
   .c1_p1_rd_data                          (test1_rd_data),
   .c1_p1_rd_full                          (test1_rd_full),
   .c1_p1_rd_empty                         (test1_rd_empty),
   .c1_p1_rd_count                         (test1_rd_count),
   .c1_p1_rd_overflow                      (test1_rd_overflow),
   .c1_p1_rd_error                         (test1_rd_error)

`endif
);      

// user interface

`ifdef SYSY_TEST  
 memc1_tb_top #
 (
   .C_NUM_DQ_PINS                           (C1_NUM_DQ_PINS),
   .C_MEM_BURST_LEN                         (C1_MEM_BURST_LEN),
   .C_MEM_NUM_COL_BITS                      (C1_MEM_NUM_COL_BITS),
   .C_p0_BEGIN_ADDRESS                      (C1_p0_BEGIN_ADDRESS),
   .C_p0_DATA_MODE                          (C1_p0_DATA_MODE),
   .C_p0_END_ADDRESS                        (C1_p0_END_ADDRESS),
   .C_p0_PRBS_EADDR_MASK_POS                (C1_p0_PRBS_EADDR_MASK_POS),
   .C_p0_PRBS_SADDR_MASK_POS                (C1_p0_PRBS_SADDR_MASK_POS),
   .C_p1_BEGIN_ADDRESS                      (C1_p1_BEGIN_ADDRESS),
   .C_p1_DATA_MODE                          (C1_p1_DATA_MODE),
   .C_p1_END_ADDRESS                        (C1_p1_END_ADDRESS),
   .C_p1_PRBS_EADDR_MASK_POS                (C1_p1_PRBS_EADDR_MASK_POS),
   .C_p1_PRBS_SADDR_MASK_POS                (C1_p1_PRBS_SADDR_MASK_POS)
   )

memc1_tb_top_inst
(
   .clk0                (c1_clk0),
   .rst0                (c1_rst0),
   .calib_done          (c1_calib_done), 
   .error               (c1_error),
   .error_status        (c1_error_status),
   .cmp_data            (c1_cmp_data),
   .cmp_data_valid      (c1_cmp_data_valid),
   .cmp_error           (c1_cmp_error),
   .vio_modify_enable   (1'b1),
   .vio_data_mode_value (3'b010),
   .vio_addr_mode_value (3'b011),
   .p0_mcb_cmd_en_o                         (c1_p0_cmd_en),
   .p0_mcb_cmd_instr_o                      (c1_p0_cmd_instr),
   .p0_mcb_cmd_bl_o                         (c1_p0_cmd_bl),
   .p0_mcb_cmd_addr_o                       (c1_p0_cmd_byte_addr),
   .p0_mcb_cmd_full_i                       (c1_p0_cmd_full),
   .p0_mcb_wr_en_o                          (c1_p0_wr_en),
   .p0_mcb_wr_mask_o                        (c1_p0_wr_mask),
   .p0_mcb_wr_data_o                        (c1_p0_wr_data),
   .p0_mcb_wr_full_i                        (c1_p0_wr_full),
   .p0_mcb_wr_fifo_counts                   (c1_p0_wr_count),
   .p0_mcb_rd_en_o                          (c1_p0_rd_en),
   .p0_mcb_rd_data_i                        (c1_p0_rd_data),
   .p0_mcb_rd_empty_i                       (c1_p0_rd_empty),
   .p0_mcb_rd_fifo_counts                   (c1_p0_rd_count),
   .p1_mcb_cmd_en_o                         (c1_p1_cmd_en),
   .p1_mcb_cmd_instr_o                      (c1_p1_cmd_instr),
   .p1_mcb_cmd_bl_o                         (c1_p1_cmd_bl),
   .p1_mcb_cmd_addr_o                       (c1_p1_cmd_byte_addr),
   .p1_mcb_cmd_full_i                       (c1_p1_cmd_full),
   .p1_mcb_wr_en_o                          (c1_p1_wr_en),
   .p1_mcb_wr_mask_o                        (c1_p1_wr_mask),
   .p1_mcb_wr_data_o                        (c1_p1_wr_data),
   .p1_mcb_wr_full_i                        (c1_p1_wr_full),
   .p1_mcb_wr_fifo_counts                   (c1_p1_wr_count),
   .p1_mcb_rd_en_o                          (c1_p1_rd_en),
   .p1_mcb_rd_data_i                        (c1_p1_rd_data),
   .p1_mcb_rd_empty_i                       (c1_p1_rd_empty),
   .p1_mcb_rd_fifo_counts                   (c1_p1_rd_count)
  

  );
`else
`endif
// ========================================================================== //
// Memory model instances                                                     // 
// ========================================================================== //

     ddr2_model_c1 #(.DEBUG(0)) u_mem_c1(
        .ck         (mcb1_dram_ck),
        .ck_n       (mcb1_dram_ck_n),
        .cke        (mcb1_dram_cke),
        .cs_n       (1'b0),
        .ras_n      (mcb1_dram_ras_n),
        .cas_n      (mcb1_dram_cas_n),
        .we_n       (mcb1_dram_we_n),
        .dm_rdqs    ({mcb1_dram_udm,mcb1_dram_dm}),
        .ba         (mcb1_dram_ba),
        .addr       (mcb1_dram_a),
        .dq         (mcb1_dram_dq),
        .dqs        ({mcb1_dram_udqs,mcb1_dram_dqs}),
        .dqs_n      ({mcb1_dram_udqs_n,mcb1_dram_dqs_n}),
        .rdqs_n     (),
        .odt        (mcb1_dram_odt)
      );
 


endmodule
